1. Field of the Invention
The present invention relates in general to the manufacture of semiconductor integrated circuits. More particularly, it relates to a process for creating a dual damascene structure in a dielectric layer without an etch stop.
2. Description of the Related Arts
In very and ultra large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material (such as silicon oxide) of the semiconductor device in a dual damascene process is patterned with several thousand openings for the conductive lines and vias which are filled with metal (such as aluminum) and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process is also used for forming multilevel metal signal lines (such as copper signal lines) in the insulating layers (such as polyimide) of the multilayer substrate on which semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which trenches are formed in a dielectric layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the trenches of single damascene, the conductive via openings also are formed. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive trenches and vias with metal at the same time, thereby eliminating process steps. In the standard dual damascene process, two photolithographic processes and two dielectric layers separated by an etch stop layer are employed to achieve the dual damascene structure.
Although the dual damascene offers advantages over other processes for forming interconnections, it has a major drawback in that the etch stop, typically silicon nitride or silicon oxynitride, considerably increases the effective capacitance and the RC delay time due to its high dielectric constant. As a result, the operational speed of the semiconductor device is decreased. Thus, improvements are needed in the dual damascene process to eliminate the use of the etch stop.
An object of the invention is to provide an improved dual damascene process for forming conductive line trenches and vias without an etch stop, thereby reducing the effective capacitance and increasing the operational speed of semiconductor devices.
To accomplish the above objective, the present invention provides a process for forming a dual damascene metal interconnect and via structure over a substrate. A via pattern is first etched in the upper half of a dielectric layer by using a hard mask overlying the dielectric layer. Then a conductive line pattern is etched in the upper half of the dielectric layer while the via pattern already present in the upper half of the layer is simultaneously transferred into the lower half. Thus, a dual damascene structure comprising via openings and metal line trenches is created in the dielectric layer without needing an etch stop.
According to an aspect of the invention, there is provided a damascene process which includes the steps of: (a) providing a device substrate having a dielectric layer thereon; (b) forming a mask layer with a via pattern overlaying the dielectric layer; (c) forming a photoresist layer with a conductive line pattern aligned with said via pattern overlaying the mask layer; (d) etching part of the way through the dielectric layer using said mask layer as an etch mask, thereby transferring said via pattern into the upper half of the dielectric layer; (e) etching said mask layer and said dielectric layer using said photoresist layer as an etch mask, thereby transferring said conductive line pattern into the upper half of the dielectric layer to form a conductive line trench, and simultaneously transferring said via pattern in the upper half of the dielectric layer into the lower half of the dielectric layer to form a via opening; and (f) filling said conductive line trench and said via opening with a conductive material.
According to another aspect of the invention, there is provided another damascene process which includes the steps of: (a) providing a device substrate having a dielectric layer thereon; (b) forming a mask layer with a via pattern overlaying the dielectric layer; (c) forming a photoresist layer with a conductive line pattern aligned with said via pattern overlaying the mask layer; (d) transferring said conductive line pattern into the upper half of the dielectric layer to form a conductive line trench, and simultaneously transferring said via pattern into the lower half of the dielectric layer to form a via opening by a single selective etching; and (e) filling said conductive line trench and said via opening with a conductive material.
In accordance with the present invention, the mask layer is preferably silicon nitride or silicon oxynitride, and preferably has a thickness of about 100 xc3x85 to 1000 xc3x85. The dielectric layer can be silicon dioxide, borosilicate glass, borophosphosilicate glass, phosphosilicate glass, or low-k materials.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description which makes reference to the accompanying drawings.